Dynamic Random Access Memory chips (DRAMs) are widely used among semiconductor memory devices because of their high density and low cost. The basic operation of a DRAM is to record data by storing bits as the presence ("1") or absence ("0") of electrical charge in memory cell capacitors. Silicon oxide is traditionally used as the dielectric layer of the memory cell capacitor of the DRAM, but recently DRAMS have been developed using a ferroelectric layer instead.
A circuit diagram of a semiconductor memory device using ferroelectric capacitors as taught by prior art is represented in FIG. 27. FIG. 27 depicts a semiconductor memory device having four memory cells 30a, 30b, 30c, 30d arranged in two rows and two columns, although a different number of memory cells could be provided. In any case, each memory cell is similarly structured, so the operation of the semiconductor memory device may be explained with respect to memory cell 30a with the understanding that corresponding operations can be applied to the other memory cells as well.
In memory cell 30a, one of a pair of ferroelectric capacitors 33a is connected through one of a pair of MOS transistors 31a to bit line 35; the other ferroelectric capacitor 33a is connected through the other MOS transistor 31a to bit line 36. The gates of both MOS transistors 31a are controlled by word line 32, and both ferroelectric capacitors 33a are connected to cell plate electrode 39. Signal line 47 supplies control signal .phi.P to MOS transistors 43, 44, either grounding or precharging bit lines 35, 36. A second signal line 49 supplies control signal .phi.S to sense amplifier 41.
In a memory cell such as 30a, comprised of two ferroelectric capacitors 33a and two MOS transistors 31a, data is written by applying logical voltages of opposite polarities to the pair of ferroelectric capacitors 33a. The stored data can then be read by reading out the residual charges from the pair of ferroelectric capacitors 33a onto the pair of bit lines 35, 36, and amplifying the potential difference between the bit lines 35, 36 with the sense amplifier 41.
The operation of the prior art semiconductor memory device of FIG. 27 can be explained in greater detail with reference to FIGS. 28 and 29. FIG. 28 shows a hysteresis curve; FIG. 29 is a timing chart of a readout operation on memory cell 30a.
As shown in FIG. 28, initially, word line 32, cell plate electrode 39, bit lines 35, 36 and signal line 49 supplying control signal .phi.S are all at a low logical voltage "L". While signal line 47 supplying control signal .phi.P is at a high logical voltage "H". To enable the memory device to read the data stored in ferroelectric capacitors 33a, signal line 47 is changed to "L", shifting bit lines 35, 36 to a floating state. Word line 32 and cell plate electrode 39 are then changed to "H", turning on MOS transistors 31a and enabling the data stored in ferroelectric capacitors 33a to be read out onto bit lines 35, 36.
The potential difference between the charges read out from ferroelectric capacitors 33a onto bit lines 35, 36 is shown in the hysteresis curve of FIG. 28. After data is stored in a ferroelectric capacitor and the power supply is cut off, the electric field is zero and the residual charges in the ferroelectric capacitor are utilized as nonvolatile data. The residual charge for high and low voltages are represented respectively by points B and E: When the data value stored in a memory cell is a "1", a first of the pair of ferroelectric capacitors stands at point B and the other stands at point E. When the data value stored in a memory cell is a "0", the situation is reversed, with the first ferroelectric capacitor at point E and the other at point B.
Still referring to FIG. 28, the slopes of straight lines L1, L2 depend on the parasitic capacitance of bit lines 35, 36: the less parasitic the capacitance, the smaller the absolute value of the slope. Points M21 and N21 are found by horizontally shifting points B and E by a magnitude of electric field produced when the voltages of word line 32 and cell plate electrode 39 are at a logical voltage "H".
The curves from the points B and E to point D represent the electrical charge held in ferroelectric capacitors 33a as the electrical field changes due to the voltage shift of word line 32 and cell plate electrode 39 from "L" to "H". When a stored data value "1" is read out onto bit line 35 from a first of the pair of ferroelectric capacitors 33a, the state of that ferroelectric capacitor 33a moves from point B to point 021, where the hysteresis curve intersects with line L1. Similarly, the state of the second ferroelectric capacitor 33a, which carries an opposite logical value from the first ferroelectric capacitor 33a, moves from point E to point P21, where the hysteresis curve intersects with line L2. Thus the read-out potential difference between the pair of bit lines 35, 36 becomes Vr21, the difference between the electric fields at point 021 and point P21.
To read the data on bit lines 35, 36, the potential difference Vr21 is amplified and signal line 49 supplying control signal .phi.S is shifted from "L" to "H". When the amplification in the sense amplifier 41 is complete, the state of bit line 35 shifts from point 021 to point Q21, and the state of bit line 36 shifts from point P21 to point D.
When the data is read, the charges in ferroelectric capacitors 33a dissipate and must be rewritten. Voltage at cell plate electrode 39 shifts from "L" to "H", moving bit line 35 from point Q21 to point A. Similarly, bit line 36 moves from point D to point E. This completes the rewriting process, and the semiconductor memory device is now restored to its initial state: word line 32 and control signal .phi.S are shifted to "L", signal line 47 is shifted to "H", and bit lines 35, 36 are returned to "L" from floating state.
If the value stored in memory cell 30a is "0" rather than "1", with the effect that the first of the pair of ferroelectric capacitors 33a stores a "0" and the other ferroelectric capacitor 33a stores a "1", the states of the bit lines 35, 36 are reversed, but the process remains the same and the potential difference remains Vr21.
The prior art semiconductor memory device described above is able to write data into its memory, as well as read and rewrite stored data from memory. However, having no means to monitor the number of readouts performed, it is impossible to limit data readout operations to a number agreed upon between the data offerer and the data user.
Moreover, a semiconductor memory device as taught by the prior art has no security feature to prevent an outsider from reading normal data stored in it. Thus, if a user fails to erase information stored as normal data in the device after completing use of that information, an outsider who obtains the device can read out that information as normal data.
Accordingly, there exists a need for a semiconductor memory device with the enhanced capability to limit the number of data readouts to a predetermined maximum limit, as well as to provide a security feature to automatically change information stored as normal data to abnormal data after the information is no longer needed by the user, in order to prevent outsiders from being able to read out information stored on the device as normal data.